library IEEE;
use IEEE.std_logic_1164.all;

entity IR is
	port(input : in std_logic_vector(31 downto 0);
		OP : out std_logic_vector(5 downto 0);
		rs : out std_logic_vector(4 downto 0);
		rt : out std_logic_vector(4 downto 0);
		rd : out std_logic_vector(4 downto 0);
		funct : out std_logic_vector(5 downto 0);
		clk : in std_logic);
end IR;

architecture mixed of IR is
	signal q : std_logic_vector(31 downto 0);
begin
	process(clk)	
	begin
		if clk'EVENT and clk='1' then
			q<=input;
		end if;
	end process;

	OP <= q(31 downto 26);
	rs <= q(25 downto 21);
	rt <= q(20 downto 16);
	rd <= q(15 downto 11);
	funct <= q(5 downto 0);
end mixed;

library IEEE;
use IEEE.std_logic_1164.all;

package mips_package1 is
	component IR
		port(input : in std_logic_vector(31 downto 0);
			OP : out std_logic_vector(5 downto 0);
			rs : out std_logic_vector(4 downto 0);
			rt : out std_logic_vector(4 downto 0);
			rd : out std_logic_vector(4 downto 0);
			funct : out std_logic_vector(5 downto 0);
			clk : in std_logic);
	end component;
end mips_package1;
